Linear-capacitance (linear-cap) varactors are used in various applications that require capacitors with variable capacitance. For example, in phase-locked oscillators, linear-cap varactors with linear gain and low Kvco (the gain of the voltage control ring oscillator) are needed.
FIG. 1 illustrates a conventional junction capacitor 100, which includes gate dielectric 102, gate electrode 104, and N+ region 106 and P+ region 108, which are located in n-well region 110. N+ region 106 is connected to gate electrode 104. Junction 112, which forms a junction capacitor, is formed between P+ region 108 and n-well region 110. The capacitance of junction capacitor 112 can be tuned by adjusting the bias voltage applied between P+ region 108 and N+ region 106. It is observed that junction capacitor 112 can only be operated under a negative bias voltage. Further, the tuning range of the capacitance of junction capacitor 112 is low.
FIG. 2 illustrates conventional NMOS varactor 200, which includes gate dielectric 202, gate electrode 204, and N+regions 206 and 208 that are located in n-well region 210. N+ regions 206 and 208 are interconnected. Varactor 200 includes capacitor 212 and 214 connected in series. Capacitor 212 is the capacitor having gate dielectric 202 as a capacitor insulator. Capacitor 214 is the capacitor having the depletion layer (not shown) that is directly under gate dielectric layer 202 as a capacitor insulator. It is observed that the capacitance of capacitor 214 is affected by the thickness of the depletion layer, which is further affected by the voltage applied between gate electrode 104 and N+ regions 206 and 208. The resulting capacitance is highly non-linear. Further, it is difficult to tune the capacitance sensitivity of varactor 200, wherein the capacitance sensitivity is the ratio of the change in the capacitance of varactor 200 to the change in the voltage applied between gate electrode 104 and N+ regions 206 and 208.